Analog-to-digital converters (ADCs) contain a mixture of analog and digital circuitry that is used to convert an analog input signal into a digital output word. The accuracy with which the digital output word represents the analog input signal is generally based on the speed, resolution and linearity of the conversion. The conversion speed must be high enough to sample the shortest analog input signal period (highest analog signal frequency) at least twice. The conversion resolution is determined by the number of bits in the digital output word and has to be large enough to resolve the maximum peak-to-peak analog input signal into a required degree of granularity. The conversion linearity has to be sufficient to operate at or preferably below a required maximum level of distortion associated with the conversion process.
Several different algorithms and architectures exist that may be employed to accomplish a conversion. These include successive approximation, sigma-delta, dual slope integrating, flash and pipeline ADCs. Of particular interest is the pipeline ADC, which typically provides a conversion every clock cycle after an initial latency period. The pipeline ADC may also provide a significant conversion resolution (12 or more bits) at high analog signal sampling rates (80 million or more samples per second).
The pipeline ADC employs a pipeline of conversion stages wherein each pipeline stage provides a subset of the total number of overall bits of resolution. Additionally, each pipeline stage typically employs a sample and hold circuit and a residual signal normalizing circuit. The sample and hold circuit employs input and feedback capacitors to track a stage input signal and then hold a particular value while an associated pipeline stage converts it to one or more bits of resolution. A residual analog signal is amplified by the residual signal normalizing circuit and presented as the input signal to the succeeding pipeline stage.
For ideal linearity, an ADC transfer curve would look like a stair case that starts and stops in the correct locations and has steps that are uniform in width and height. A differential non-linearity (DNL) arises when the stair steps (representing particular conversion codes) are not the same widths. These stair widths may be a half-width too wide or too narrow based on a one half least significant bit (LSB) error in the conversion. A DNL also arises when a conversion code is erroneously skipped (a “missing code” where DNL equals −1 LSB) resulting in a double stair width. An integral non-linearity (INL) may be defined as a running summation of these various DNL errors.
The capability to emulate linearity errors is valuable both as design and testing tools. Physical, empirical or “a priori” models may be used to provide this capability. A physical model usually requires the application of engineering judgement to approximate the performance of a device. This makes its application more difficult in all but simple applications. An empirical model typically recjuires the development of statistical data taken from actual devices. To be reliable, this data should be noise-free and taken from as large a sample space as possible. A priori models are usually based on an investigative system employing a mathematical function.
A major transition is defined as a location in a converter design where a discontinuity may arise thereby affecting both DNL and INL directly. For example, the major transitions of a successive approximation ADC are always located in a predictable 2n locations, where n is the number of bits defining its resolution. Rademacher functions are sequential functions that may be employed in an a priori model to provide transition-effect linearity errors associated with successive approximation ADCs. Rademacher functions accomplish this purpose by providing the locations of the major carry transitions associated with the successive approximation algorithm. However, the Rademacher functions are not suited for pipeline ADCs, since their transition locations vary depending on a specific pipeline ADC design.
Accordingly, what is needed in the art is a way to apply an a priori model in ascertaining linearity errors for an ADC having a pipeline structure.